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(parent: 62037ff) | patch
drm/i915/tgl: Add HDC Pipeline Flush
authorMika Kuoppala <mika.kuoppala@linux.intel.com>
Tue, 15 Oct 2019 15:44:41 +0000 (18:44 +0300)
committerChris Wilson <chris@chris-wilson.co.uk>
Tue, 15 Oct 2019 17:15:59 +0000 (18:15 +0100)
commit4aa0b5d457f5d29522b5db4aeb4587fc4dc24054
treec8f47049dabe546301b0aae8a9d0957272e87f88tree | snapshot
parent62037ffff229b7d94f1db5ef8d2e2ec819832ef3commit | diff
drm/i915/tgl: Add HDC Pipeline Flush

Add hdc pipeline flush to ensure memory state is coherent
in L3 when we are done.

v2: Flush also in breadcrumbs (Chris)

Cc: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Link: https://patchwork.freedesktop.org/patch/msgid/20191015154449.10338-3-mika.kuoppala@linux.intel.com
drivers/gpu/drm/i915/gt/intel_gpu_commands.h diff | blob | history
drivers/gpu/drm/i915/gt/intel_lrc.c diff | blob | history
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