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[AMDGPU] Add new pseudos for indirect addressing with VGPR Indexing
authorAustin Kerbow <Austin.Kerbow@amd.com>
Fri, 6 Nov 2020 07:43:58 +0000 (23:43 -0800)
committerAustin Kerbow <Austin.Kerbow@amd.com>
Tue, 8 Dec 2020 20:24:12 +0000 (12:24 -0800)
commit4aa842a800b53806a9e25f03b4e21f6879801a38
tree92543d518e575ca4a2849e08d1d75309a6967e00
parent98bca0a60574c4276cfc85833fe29d8f4beff7f6
[AMDGPU] Add new pseudos for indirect addressing with VGPR Indexing

It is possible for copies or spills to be inserted in the middle of indirect
addressing sequences which use VGPR indexing. Spills to accvgprs could be
effected by the indexing mode.

Add new pseudo instructions that are expanded after register allocation to avoid
the problematic spill or copy placement.

Differential Revision: https://reviews.llvm.org/D91048
13 files changed:
llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
llvm/lib/Target/AMDGPU/SIISelLowering.cpp
llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
llvm/lib/Target/AMDGPU/SIInstrInfo.h
llvm/lib/Target/AMDGPU/SIInstructions.td
llvm/lib/Target/AMDGPU/SIMemoryLegalizer.cpp
llvm/test/CodeGen/AMDGPU/GlobalISel/extractelement.i128.ll
llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-extract-vector-elt.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-insert-vector-elt.mir
llvm/test/CodeGen/AMDGPU/expand-si-indirect.mir [new file with mode: 0644]
llvm/test/CodeGen/AMDGPU/indirect-addressing-si-gfx9.ll
llvm/test/CodeGen/AMDGPU/indirect-addressing-si.ll
llvm/test/CodeGen/AMDGPU/indirect-addressing-term.ll