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PCI: exynos: Split into Synopsys part and Exynos part
authorJingoo Han <jg1.han@samsung.com>
Wed, 31 Jul 2013 08:14:10 +0000 (17:14 +0900)
committerBjorn Helgaas <bhelgaas@google.com>
Mon, 12 Aug 2013 18:18:20 +0000 (12:18 -0600)
commit4b1ced841b2e31470ae4bb47988891754ce4d8c7
tree8fdf59944d73d9b946922e9d3c42239acce6aa8f
parent5477a33b51b7282aca731213dc592b5f0c4e7c13
PCI: exynos: Split into Synopsys part and Exynos part

Exynos PCIe IP consists of Synopsys specific part and Exynos
specific part. Only core block is a Synopsys Designware part;
other parts are Exynos specific.

Also, the Synopsys Designware part can be shared with other
platforms; thus, it can be split two parts such as Synopsys
Designware part and Exynos specific part.

Signed-off-by: Jingoo Han <jg1.han@samsung.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Cc: Pratyush Anand <pratyush.anand@st.com>
Cc: Mohit KUMAR <Mohit.KUMAR@st.com>
Documentation/devicetree/bindings/pci/designware-pcie.txt
arch/arm/boot/dts/exynos5440.dtsi
drivers/pci/host/Makefile
drivers/pci/host/pci-exynos.c [new file with mode: 0644]
drivers/pci/host/pcie-designware.c
drivers/pci/host/pcie-designware.h [new file with mode: 0644]