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[X86] Teach X86FixupBWInsts to promote MOV8rr/MOV16rr to MOV32rr.
authorAhmed Bougacha <ahmed.bougacha@gmail.com>
Sat, 7 May 2016 01:11:17 +0000 (01:11 +0000)
committerAhmed Bougacha <ahmed.bougacha@gmail.com>
Sat, 7 May 2016 01:11:17 +0000 (01:11 +0000)
commit4c690f39540a2f2a3b0bd3347e82aa57afd2ff16
tree3e821948f373261010bca73a7689567f1d8deb76
parent9ea4c644e105dc6636a4aeb3c32d2c71ad3f99e5
[X86] Teach X86FixupBWInsts to promote MOV8rr/MOV16rr to MOV32rr.

This re-applies r268760, reverted in r268794.
Fixes http://llvm.org/PR27670

The original imp-defs assertion was way overzealous: forward all
implicit operands, except imp-defs of the new super-reg def (r268787
for GR64, but also possible for GR16->GR32), or imp-uses of the new
super-reg use.
While there, mark the source use as Undef, and add an imp-use of the
old source reg: that should cover any case of dead super-regs.

At the stage the pass runs, flags are unlikely to matter anyway;
still, let's be as correct as possible.

Also add MIR tests for the various interesting cases.

Original commit message:
Codesize is less (16) or equal (8), and we avoid partial
dependencies.

Differential Revision: http://reviews.llvm.org/D19999

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@268831 91177308-0d34-0410-b5e6-96231b3b80d8
18 files changed:
lib/Target/X86/X86FixupBWInsts.cpp
test/CodeGen/X86/2011-06-14-PreschedRegalias.ll
test/CodeGen/X86/anyext.ll
test/CodeGen/X86/avx512-calling-conv.ll
test/CodeGen/X86/avx512-mask-op.ll
test/CodeGen/X86/avx512-select.ll
test/CodeGen/X86/avx512dq-mask-op.ll
test/CodeGen/X86/cmovcmov.ll
test/CodeGen/X86/fixup-bw-copy.ll [new file with mode: 0644]
test/CodeGen/X86/fixup-bw-copy.mir [new file with mode: 0644]
test/CodeGen/X86/float-conv-elim.ll
test/CodeGen/X86/machine-combiner-int.ll
test/CodeGen/X86/opt-ext-uses.ll
test/CodeGen/X86/pr23664.ll
test/CodeGen/X86/vector-bitreverse.ll
test/CodeGen/X86/vector-idiv-sdiv-512.ll
test/CodeGen/X86/vector-idiv-udiv-512.ll
test/CodeGen/X86/xaluo.ll