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media: ccs-pll: Add support for extended input PLL clock divider
authorSakari Ailus <sakari.ailus@linux.intel.com>
Tue, 23 Jun 2020 11:40:32 +0000 (13:40 +0200)
committerMauro Carvalho Chehab <mchehab+huawei@kernel.org>
Mon, 7 Dec 2020 14:56:17 +0000 (15:56 +0100)
commit4e1e8d240dff96bd8dd2c00c5fcd7f04088ace3c
treeb5738c25e951292d6dd82a158af6d0ef54f73a88
parentae502e08f45e47460406ab5c5fd2167a1011499a
media: ccs-pll: Add support for extended input PLL clock divider

CCS allows odd PLL dividers other than 1, granted that the corresponding
capability bit is set. Support this both in the PLL calculator and the CCS
driver.

Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com>
Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
drivers/media/i2c/ccs-pll.c
drivers/media/i2c/ccs-pll.h
drivers/media/i2c/ccs/ccs-core.c