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(parent: 91693cb) | patch
drm/msm/dsi_pll_7nm: restore VCO rate during restore_state
authorDmitry Baryshkov <dmitry.baryshkov@linaro.org>
Thu, 15 Oct 2020 19:03:29 +0000 (22:03 +0300)
committerRob Clark <robdclark@chromium.org>
Wed, 4 Nov 2020 16:26:25 +0000 (08:26 -0800)
commit5047ab95bb7db0e7b2ecfd5e9bcafc7fd822c652
treee5af3107970c427b9100d2b50e1a3cfd8ab234c4tree | snapshot
parent91693cbc13c2eebaa2bffb685cc7cb6d561f33eccommit | diff
drm/msm/dsi_pll_7nm: restore VCO rate during restore_state

PHY disable/enable resets PLL registers to default values. Thus in
addition to restoring several registers we also need to restore VCO rate
settings.

Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Fixes: 1ef7c99d145c ("drm/msm/dsi: add support for 7nm DSI PHY/PLL")
Signed-off-by: Rob Clark <robdclark@chromium.org>
drivers/gpu/drm/msm/dsi/pll/dsi_pll_7nm.c diff | blob | history
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