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drm/i915/xehpsdv: Define MOCS table for XeHP SDV
authorLucas De Marchi <lucas.demarchi@intel.com>
Sat, 4 Sep 2021 00:35:43 +0000 (17:35 -0700)
committerMatt Roper <matthew.d.roper@intel.com>
Tue, 14 Sep 2021 22:27:07 +0000 (15:27 -0700)
commit50bc6486a8f12643624cd3c48cd67fe49873849a
treebf5c352c07502991df3ccfd7775adc042625a6ac
parent43192617f7816bb74584c1df06f57363afd15337
drm/i915/xehpsdv: Define MOCS table for XeHP SDV

Like DG1, XeHP SDV doesn't have LLC/eDRAM control values due to being a
dgfx card. XeHP SDV adds 2 more bits: L3_GLBGO to "push the Go point to
memory for L3 destined transaction" and L3_LKP to "enable Lookup for
uncacheable accesses".

Bspec: 45101
Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
Signed-off-by: Stuart Summers <stuart.summers@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: Clint Taylor <Clinton.A.Taylor@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20210904003544.2422282-2-matthew.d.roper@intel.com
drivers/gpu/drm/i915/gt/intel_mocs.c