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target/riscv: remove force HS exception
authorJose Martins <josemartins90@gmail.com>
Tue, 26 Oct 2021 14:51:26 +0000 (15:51 +0100)
committerAlistair Francis <alistair@alistair23.me>
Fri, 29 Oct 2021 06:54:45 +0000 (16:54 +1000)
commit50d160876414e91e51ac718ac6edea6dbadf4694
tree1530ca6d918f2d8fb1fc5e089685e29f0440141c
parent487a99551ae903fc83a878d4cbc6d853e17ad252
target/riscv: remove force HS exception

There is no need to "force an hs exception" as the current privilege
level, the state of the global ie and of the delegation registers should
be enough to route the interrupt to the appropriate privilege level in
riscv_cpu_do_interrupt. The is true for both asynchronous and
synchronous exceptions, specifically, guest page faults which must be
hardwired to zero hedeleg. As such the hs_force_except mechanism can be
removed.

Signed-off-by: Jose Martins <josemartins90@gmail.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20211026145126.11025-3-josemartins90@gmail.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
target/riscv/cpu.h
target/riscv/cpu_bits.h
target/riscv/cpu_helper.c