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(parent: 6557447) | patch
[X86][BtVer2] Fix WriteFShuffle256 schedule write info.
authorAndrea Di Biagio <Andrea_DiBiagio@sn.scee.net>
Fri, 31 Aug 2018 08:30:47 +0000 (08:30 +0000)
committerAndrea Di Biagio <Andrea_DiBiagio@sn.scee.net>
Fri, 31 Aug 2018 08:30:47 +0000 (08:30 +0000)
commit53c157a2904163797c88e5a237c74acddc6898e0
treec6b7c30b62177e621a7a03d07c3ff5d9dbe9d748tree | snapshot
parent6557447c4250bb9ef6b402eeb957840493f15d83commit | diff
[X86][BtVer2] Fix WriteFShuffle256 schedule write info.

This patch fixes the number of micro opcodes, and processor resource cycles for
the following AVX instructions:

vinsertf128rr/rm
vperm2f128rr/rm
vbroadcastf128

Tests have been regenerated using the usual scripts in the llvm/utils directory.

Differential Revision: https://reviews.llvm.org/D51492

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@341185 91177308-0d34-0410-b5e6-96231b3b80d8
lib/Target/X86/X86ScheduleBtVer2.td diff | blob | history
test/CodeGen/X86/avx-schedule.ll diff | blob | history
test/tools/llvm-mca/X86/BtVer2/resources-avx1.s diff | blob | history
external/llvm
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