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ART: Fix GenReduceVector and GenSetVector
authorUdayan Banerji <udayan.banerji@intel.com>
Fri, 26 Sep 2014 17:41:47 +0000 (10:41 -0700)
committerUdayan Banerji <udayan.banerji@intel.com>
Fri, 26 Sep 2014 17:41:47 +0000 (10:41 -0700)
commit53cec00aa6789382621a53b33b13f45bd27148ca
tree54739a2f5db0d11267c0fc108dfd56257efddb51tree | snapshot
parent628a74f9365f7d18dbd1fcc6b2f2661780574b4fcommit | diff
ART: Fix GenReduceVector and GenSetVector

For GenReduceVector:
We now correctly load non-wide values for non-wide destination registers,
and generate reg-reg and reg-mem forms of pextr correctly.

For GenSetVector:
We use the correct opcode from loading into an xmm from a 64-bit GPR

Change-Id: I0a01d1f0b12b32a0dee8f79a0139ffcf6d6cb4d5
Signed-off-by: Udayan Banerji <udayan.banerji@intel.com>
compiler/dex/quick/x86/target_x86.cc diff | blob | history
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