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ARM: dts: ls1021a: Remove num-lanes property from PCIe nodes
authorHou Zhiqiang <Zhiqiang.Hou@nxp.com>
Tue, 20 Aug 2019 07:28:55 +0000 (07:28 +0000)
committerLorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Thu, 22 Aug 2019 17:20:47 +0000 (18:20 +0100)
commit568adba9eb201875bc561745e0f19b831b7e2bbc
tree8fa07fbc565b26310dd47775ba5ef5709dc2d14c
parent66de33f09fd97201847de7e1e2ec8a117242e1d6
ARM: dts: ls1021a: Remove num-lanes property from PCIe nodes

Remove the num-lanes property to avoid the driver setting the
link width.

On FSL Layerscape SoCs, the number of lanes assigned to PCIe
controller is not fixed, it is determined by the selected SerDes
protocol in the RCW (Reset Configuration Word).

The PCIe link training is completed automatically through the selected
SerDes protocol - the link width set-up is updated by hardware after
power on reset, so the num-lanes property is not needed for Layerscape
PCIe.

The current num-lanes property was added erroneously, which actually
indicates the maximum lanes the PCIe controller can support up to,
instead of the lanes assigned to the PCIe controller. The link width set
by SerDes protocol will be overridden by the num-lanes property, hence
the subsequent re-training will fail when the assigned lanes do not
match the value in the num-lanes property.

Remove the property to fix the issue.

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Reviewed-by: Andrew Murray <andrew.murray@arm.com>
arch/arm/boot/dts/ls1021a.dtsi