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(parent: cac8f5d) | patch
media: ccs: Add support for lane speed model
authorSakari Ailus <sakari.ailus@linux.intel.com>
Wed, 23 Sep 2020 10:16:03 +0000 (12:16 +0200)
committerMauro Carvalho Chehab <mchehab+huawei@kernel.org>
Mon, 7 Dec 2020 14:53:05 +0000 (15:53 +0100)
commit585e17c98407e1c2ec7735f37379e96cf0f74e3a
tree9647d9d194a8f7e1dedb537f4ece298e4254c332tree | snapshot
parentcac8f5d28e56c405befd1613fc38c962aaf69f30commit | diff
media: ccs: Add support for lane speed model

Convey the relevant PLL flags to the PLL calculator. Also the lane speed
model affects how the link rate is calculated on the CSI-2 bus, as the
rate is total of all lanes.

Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com>
Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
drivers/media/i2c/ccs/ccs-core.c diff | blob | history
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