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[DAGCombiner] simplify div/rem-by-0
authorSanjay Patel <spatel@rotateright.com>
Mon, 6 Mar 2017 16:36:42 +0000 (16:36 +0000)
committerSanjay Patel <spatel@rotateright.com>
Mon, 6 Mar 2017 16:36:42 +0000 (16:36 +0000)
commit58868f1c75dbc9a2e9a875008315c531f28b2d00
tree8344f1bd0d7d75bec0c90829d4f82d06c9cb3ad4
parent5645eb34af0a91046107c432dd7545922c433ebb
[DAGCombiner] simplify div/rem-by-0

Refactoring of duplicated code and more fixes to follow.

This is motivated by the post-commit comments for r296699:
http://lists.llvm.org/pipermail/llvm-commits/Week-of-Mon-20170306/435182.html

Ie, we can crash if we're missing obvious simplifications like this that
exist in the IR simplifier or if these occur later than expected.

The x86 change for non-splat division shows a potential opportunity to improve
vector codegen: we assumed that since only one lane had meaningful results, we
should do the math in scalar. But that means moving back and forth from vector
registers.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@297026 91177308-0d34-0410-b5e6-96231b3b80d8
lib/CodeGen/SelectionDAG/DAGCombiner.cpp
test/CodeGen/X86/div-rem-simplify.ll
test/CodeGen/X86/vec_sdiv_to_shift.ll