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cadence_gem: Correct the interupt logic
authorAlistair Francis <alistair.francis@xilinx.com>
Thu, 20 Apr 2017 16:32:29 +0000 (17:32 +0100)
committerPeter Maydell <peter.maydell@linaro.org>
Thu, 20 Apr 2017 16:39:17 +0000 (17:39 +0100)
commit596b6f51b71eb1dd6f603b3f5aeb0a2f9300b21f
tree47863821f83234cf7145de9fb7428e6a6870925e
parentdacc0566acda512ebaf18ad051b387a56a3f7253
cadence_gem: Correct the interupt logic

This patch fixes two mistakes in the interrupt logic.

First we only trigger single-queue or multi-queue interrupts if the status
register is set. This logic was already used for non multi-queue interrupts
but it also applies to multi-queue interrupts.

Secondly we need to lower the interrupts if the ISR isn't set. As part
of this we can remove the other interrupt lowering logic and consolidate
it inside gem_update_int_status().

Signed-off-by: Alistair Francis <alistair.francis@xilinx.com>
Message-id: 438bcc014f8f8a2f8f68f322cb6a53f4c04688c2.1491947224.git.alistair.francis@xilinx.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
hw/net/cadence_gem.c