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(parent: 966ee94) | patch
nvc0/ir: limit max number of regs based on availability in SM
authorIlia Mirkin <imirkin@alum.mit.edu>
Sat, 28 May 2016 18:28:07 +0000 (14:28 -0400)
committerEmil Velikov <emil.l.velikov@gmail.com>
Wed, 15 Jun 2016 08:29:14 +0000 (09:29 +0100)
commit59841f5466aa1b645814ecb6bd5f3dbbee80cb99
tree83944d23584b8f49c49382bfe30523949cf9f879tree | snapshot
parent966ee945580da266d52ec5cf53f7c4646dbf97d6commit | diff
nvc0/ir: limit max number of regs based on availability in SM

This effectively limits registers to 32 and 64 for fermi and kepler when
1024 threads are used, but allows the full amount to be used with
smaller thread sizes.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
(cherry picked from commit 1f895caba0accc0af3e637d6193ac0b673ce98bc)
src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nvc0.cpp diff | blob | history
src/gallium/drivers/nouveau/codegen/nv50_ir_target_nvc0.cpp diff | blob | history
external/mesa
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