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[RISCV] Initial codegen support for ALU operations
authorAlex Bradbury <asb@lowrisc.org>
Thu, 19 Oct 2017 21:37:38 +0000 (21:37 +0000)
committerAlex Bradbury <asb@lowrisc.org>
Thu, 19 Oct 2017 21:37:38 +0000 (21:37 +0000)
commit5a3d179fab70138a1cb63a8d7c4a407dbb7dba6e
treee50f04a5ea2113534abebbd84e3300b3c5dc5982tree | snapshot
parentab16d0abcd68c515720e0da86db48e36db562d3fcommit | diff
[RISCV] Initial codegen support for ALU operations

This adds the minimum necessary to support codegen for simple ALU operations
on RV32. Prolog and epilog insertion, support for memory operations etc etc
follow in future patches.

Leave guessInstructionProperties=1 until https://reviews.llvm.org/D37065 is
reviewed and lands.

Differential Revision: https://reviews.llvm.org/D29933

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@316188 91177308-0d34-0410-b5e6-96231b3b80d8
24 files changed:
lib/Target/RISCV/CMakeLists.txt diff | blob | history
lib/Target/RISCV/LLVMBuild.txt diff | blob | history
lib/Target/RISCV/RISCV.h [new file with mode: 0644] blob
lib/Target/RISCV/RISCV.td diff | blob | history
lib/Target/RISCV/RISCVAsmPrinter.cpp [new file with mode: 0644] blob
lib/Target/RISCV/RISCVCallingConv.td [new file with mode: 0644] blob
lib/Target/RISCV/RISCVFrameLowering.cpp [new file with mode: 0644] blob
lib/Target/RISCV/RISCVFrameLowering.h [new file with mode: 0644] blob
lib/Target/RISCV/RISCVISelDAGToDAG.cpp [new file with mode: 0644] blob
lib/Target/RISCV/RISCVISelLowering.cpp [new file with mode: 0644] blob
lib/Target/RISCV/RISCVISelLowering.h [new file with mode: 0644] blob
lib/Target/RISCV/RISCVInstrInfo.cpp [new file with mode: 0644] blob
lib/Target/RISCV/RISCVInstrInfo.h [new file with mode: 0644] blob
lib/Target/RISCV/RISCVInstrInfo.td diff | blob | history
lib/Target/RISCV/RISCVMCInstLower.cpp [new file with mode: 0644] blob
lib/Target/RISCV/RISCVRegisterInfo.cpp [new file with mode: 0644] blob
lib/Target/RISCV/RISCVRegisterInfo.h [new file with mode: 0644] blob
lib/Target/RISCV/RISCVRegisterInfo.td diff | blob | history
lib/Target/RISCV/RISCVSubtarget.cpp [new file with mode: 0644] blob
lib/Target/RISCV/RISCVSubtarget.h [new file with mode: 0644] blob
lib/Target/RISCV/RISCVTargetMachine.cpp diff | blob | history
lib/Target/RISCV/RISCVTargetMachine.h diff | blob | history
test/CodeGen/RISCV/alu32.ll [new file with mode: 0644] blob
test/CodeGen/RISCV/lit.local.cfg [new file with mode: 0644] blob
external/llvm
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