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target/riscv: Add itrigger support when icount is enabled
authorLIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Thu, 13 Oct 2022 06:29:44 +0000 (14:29 +0800)
committerAlistair Francis <alistair.francis@wdc.com>
Fri, 6 Jan 2023 00:42:55 +0000 (10:42 +1000)
commit5a4ae64cac49564354cd6f17598840e4af70e4f5
treea144bc9602b9e359340903c3de927cccd61bc96a
parent2c9d747121aa9f8f0494b9e3136a22a1c3a8b2a3
target/riscv: Add itrigger support when icount is enabled

The max count in itrigger can be 0x3FFF, which will cause a no trivial
translation and execution overload.

When icount is enabled, QEMU provides API that can fetch guest
instruction number. Thus, we can set an timer for itrigger with
the count as deadline.

Only when timer expires or priviledge mode changes, do lazy update
to count.

Signed-off-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20221013062946.7530-3-zhiwei_liu@linux.alibaba.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
target/riscv/cpu.h
target/riscv/cpu_helper.c
target/riscv/debug.c
target/riscv/debug.h