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[X86] Add an extra store address cycle to WriteRMW in the Sandy Bridge/Broadwell...
authorCraig Topper <craig.topper@intel.com>
Fri, 6 Apr 2018 16:16:46 +0000 (16:16 +0000)
committerCraig Topper <craig.topper@intel.com>
Fri, 6 Apr 2018 16:16:46 +0000 (16:16 +0000)
commit5a864681b8752f2cab3b01cdc9116eff095afc70
treed7e8f6e02bd27a203148e5ef59a251c340b4e78f
parentb4cde9307b55ff01e7c3f1d7e12eff086aa2179e
[X86] Add an extra store address cycle to WriteRMW in the Sandy Bridge/Broadwell/Haswell/Skylake scheduler model.

Even those the address was calculated for the load, its calculated again for the store.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329415 91177308-0d34-0410-b5e6-96231b3b80d8
lib/Target/X86/X86SchedBroadwell.td
lib/Target/X86/X86SchedHaswell.td
lib/Target/X86/X86SchedSandyBridge.td
lib/Target/X86/X86SchedSkylakeClient.td
lib/Target/X86/X86SchedSkylakeServer.td