git.osdn.net Git - android-x86/external-llvm.git/commit

(root) / android-x86 / external-llvm.git / commit

author	Matt Arsenault <Matthew.Arsenault@amd.com>
	Wed, 19 Jun 2019 00:25:39 +0000 (00:25 +0000)
committer	Matt Arsenault <Matthew.Arsenault@amd.com>
	Wed, 19 Jun 2019 00:25:39 +0000 (00:25 +0000)
commit	5b56cc85b0ffae025723062f612739de6a75f522
tree	e0fe8ea0b54ca67506cf9bb6d89c77c843cdfb34	tree \| snapshot
parent	307315e0e9566fc96d47fcb35b42857988c48d0f	commit \| diff

Rename ExpandISelPseudo->FinalizeISel, delay register reservation

This allows targets to make more decisions about reserved registers
after isel. For example, now it should be certain there are calls or
stack objects in the frame or not, which could have been introduced by
legalization.

Patch by Matthias Braun

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363757 91177308-0d34-0410-b5e6-96231b3b80d8

102 files changed:

include/llvm/CodeGen/Passes.h		diff \| blob \| history
include/llvm/InitializePasses.h		diff \| blob \| history
lib/CodeGen/CMakeLists.txt		diff \| blob \| history
lib/CodeGen/CodeGen.cpp		diff \| blob \| history
lib/CodeGen/FinalizeISel.cpp	[moved from lib/CodeGen/ExpandISelPseudos.cpp with 68% similarity]	diff \| blob \| history
lib/CodeGen/MachineVerifier.cpp		diff \| blob \| history
lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp		diff \| blob \| history
lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp		diff \| blob \| history
lib/CodeGen/TargetPassConfig.cpp		diff \| blob \| history
lib/Target/AMDGPU/AMDGPUTargetMachine.cpp		diff \| blob \| history
lib/Target/X86/X86ISelLowering.cpp		diff \| blob \| history
test/CodeGen/AArch64/GlobalISel/gisel-commandline-option-fastisel.ll		diff \| blob \| history
test/CodeGen/AArch64/GlobalISel/gisel-commandline-option.ll		diff \| blob \| history
test/CodeGen/AArch64/O0-pipeline.ll		diff \| blob \| history
test/CodeGen/AArch64/O3-pipeline.ll		diff \| blob \| history
test/CodeGen/AArch64/apple-latest-cpu.ll		diff \| blob \| history
test/CodeGen/AArch64/arm64-fast-isel-rem.ll		diff \| blob \| history
test/CodeGen/AArch64/fast-isel-dbg.ll		diff \| blob \| history
test/CodeGen/AArch64/tail-call-unused-zext.ll		diff \| blob \| history
test/CodeGen/AMDGPU/si-instr-info-correct-implicit-operands.ll		diff \| blob \| history
test/CodeGen/ARM/GlobalISel/pr35375.ll		diff \| blob \| history
test/CodeGen/ARM/O3-pipeline.ll		diff \| blob \| history
test/CodeGen/ARM/Windows/dbzchk.ll		diff \| blob \| history
test/CodeGen/ARM/Windows/vla-cpsr.ll		diff \| blob \| history
test/CodeGen/ARM/copy-by-struct-i32.ll		diff \| blob \| history
test/CodeGen/Generic/MachineBranchProb.ll		diff \| blob \| history
test/CodeGen/Hexagon/call-v4.ll		diff \| blob \| history
test/CodeGen/MIR/AArch64/print-parse-verify-failedISel-property.mir		diff \| blob \| history
test/CodeGen/MIR/AMDGPU/machine-function-info.ll		diff \| blob \| history
test/CodeGen/MIR/Generic/multiRunPass.mir		diff \| blob \| history
test/CodeGen/Mips/buildpairf64-extractelementf64-implicit-sp.ll		diff \| blob \| history
test/CodeGen/Mips/indirect-jump-hazard/guards-verify-call.mir		diff \| blob \| history
test/CodeGen/Mips/indirect-jump-hazard/guards-verify-tailcall.mir		diff \| blob \| history
test/CodeGen/Mips/instverify/dext-pos.mir		diff \| blob \| history
test/CodeGen/Mips/instverify/dext-size.mir		diff \| blob \| history
test/CodeGen/Mips/instverify/dextm-pos-size.mir		diff \| blob \| history
test/CodeGen/Mips/instverify/dextm-pos.mir		diff \| blob \| history
test/CodeGen/Mips/instverify/dextm-size.mir		diff \| blob \| history
test/CodeGen/Mips/instverify/dextu-pos-size.mir		diff \| blob \| history
test/CodeGen/Mips/instverify/dextu-pos.mir		diff \| blob \| history
test/CodeGen/Mips/instverify/dextu-size-valid.mir		diff \| blob \| history
test/CodeGen/Mips/instverify/dextu-size.mir		diff \| blob \| history
test/CodeGen/Mips/instverify/dins-pos-size.mir		diff \| blob \| history
test/CodeGen/Mips/instverify/dins-pos.mir		diff \| blob \| history
test/CodeGen/Mips/instverify/dins-size.mir		diff \| blob \| history
test/CodeGen/Mips/instverify/dinsm-pos-size.mir		diff \| blob \| history
test/CodeGen/Mips/instverify/dinsm-pos.mir		diff \| blob \| history
test/CodeGen/Mips/instverify/dinsm-size.mir		diff \| blob \| history
test/CodeGen/Mips/instverify/dinsu-pos-size.mir		diff \| blob \| history
test/CodeGen/Mips/instverify/dinsu-pos.mir		diff \| blob \| history
test/CodeGen/Mips/instverify/dinsu-size.mir		diff \| blob \| history
test/CodeGen/Mips/instverify/ext-pos-size.mir		diff \| blob \| history
test/CodeGen/Mips/instverify/ext-pos.mir		diff \| blob \| history
test/CodeGen/Mips/instverify/ext-size.mir		diff \| blob \| history
test/CodeGen/Mips/instverify/ins-pos-size.mir		diff \| blob \| history
test/CodeGen/Mips/instverify/ins-pos.mir		diff \| blob \| history
test/CodeGen/Mips/instverify/ins-size.mir		diff \| blob \| history
test/CodeGen/Mips/micromips-eva.mir		diff \| blob \| history
test/CodeGen/Mips/micromips-target-external-symbol-reloc.ll		diff \| blob \| history
test/CodeGen/Mips/mirparser/target-flags-pic-mxgot-tls.mir		diff \| blob \| history
test/CodeGen/Mips/mirparser/target-flags-pic-o32.mir		diff \| blob \| history
test/CodeGen/Mips/mirparser/target-flags-pic.mir		diff \| blob \| history
test/CodeGen/Mips/mirparser/target-flags-static-tls.mir		diff \| blob \| history
test/CodeGen/Mips/unaligned-memops-mapping.mir		diff \| blob \| history
test/CodeGen/Mips/unaligned-memops.ll		diff \| blob \| history
test/CodeGen/PowerPC/debuginfo-split-int.ll		diff \| blob \| history
test/CodeGen/SystemZ/cc-liveness.ll		diff \| blob \| history
test/CodeGen/SystemZ/debuginstr-02.mir		diff \| blob \| history
test/CodeGen/X86/MachineBranchProb.ll		diff \| blob \| history
test/CodeGen/X86/O0-pipeline.ll		diff \| blob \| history
test/CodeGen/X86/O3-pipeline.ll		diff \| blob \| history
test/CodeGen/X86/catchpad-weight.ll		diff \| blob \| history
test/CodeGen/X86/fast-isel-fneg-kill.ll		diff \| blob \| history
test/CodeGen/X86/fixed-stack-di-mir.ll		diff \| blob \| history
test/CodeGen/X86/i16lshr8pat.ll		diff \| blob \| history
test/CodeGen/X86/inline-asm-avx512f-x-constraint.ll		diff \| blob \| history
test/CodeGen/X86/inline-asm-default-clobbers.ll		diff \| blob \| history
test/CodeGen/X86/pr39896.ll		diff \| blob \| history
test/CodeGen/X86/sjlj-shadow-stack-liveness.mir		diff \| blob \| history
test/CodeGen/X86/sqrt-fastmath-mir.ll		diff \| blob \| history
test/CodeGen/X86/stack-protector-weight.ll		diff \| blob \| history
test/CodeGen/X86/switch-edge-weight.ll		diff \| blob \| history
test/CodeGen/X86/switch-jump-table.ll		diff \| blob \| history
test/CodeGen/X86/switch-lower-peel-top-case.ll		diff \| blob \| history
test/CodeGen/X86/vecloadextract.ll		diff \| blob \| history
test/CodeGen/X86/vmaskmov-offset.ll		diff \| blob \| history
test/CodeGen/X86/xor-combine-debugloc.ll		diff \| blob \| history
test/DebugInfo/ARM/float-stack-arg.ll		diff \| blob \| history
test/DebugInfo/Generic/linear-dbg-value.ll		diff \| blob \| history
test/DebugInfo/X86/dbg-value-arg-movement.ll		diff \| blob \| history
test/DebugInfo/X86/dbg-value-frame-index-2.ll		diff \| blob \| history
test/DebugInfo/X86/dbg-value-funcarg.ll		diff \| blob \| history
test/DebugInfo/X86/dbg-value-funcarg2.ll		diff \| blob \| history
test/DebugInfo/X86/pr40427.ll		diff \| blob \| history
test/DebugInfo/X86/safestack-byval.ll		diff \| blob \| history
test/DebugInfo/X86/sdag-dangling-dbgvalue.ll		diff \| blob \| history
test/DebugInfo/X86/sdag-dbgvalue-phi-use-1.ll		diff \| blob \| history
test/DebugInfo/X86/sdag-dbgvalue-phi-use-2.ll		diff \| blob \| history
test/DebugInfo/X86/sdag-dbgvalue-phi-use-3.ll		diff \| blob \| history
test/DebugInfo/X86/sdag-dbgvalue-phi-use-4.ll		diff \| blob \| history
test/DebugInfo/X86/sdag-dbgvalue-ssareg.ll		diff \| blob \| history
test/DebugInfo/X86/sdag-ir-salvage.ll		diff \| blob \| history

external/llvm

RSS Atom

About OSDN

Find Software

Develop Software

Help