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[AArch64] Register passes so they can be run by llc
authorDiana Picus <diana.picus@linaro.org>
Mon, 1 Aug 2016 05:56:57 +0000 (05:56 +0000)
committerDiana Picus <diana.picus@linaro.org>
Mon, 1 Aug 2016 05:56:57 +0000 (05:56 +0000)
commit5bfb1b8c4ef15650468c6985d4ca87cfecbe3bfc
tree1c35b7e0578b95c963b905a25712957c11099793
parent87efa54747891e7a8c34d401ddc7e3176e306efe
[AArch64] Register passes so they can be run by llc

Initialize all AArch64-specific passes in the TargetMachine so they can be run
by llc. This can lead to conflicts in opt with some command line options that
share the same name as the pass, so I took this opportunity to do some cleanups:
* rename all relevant command line options from "aarch64-blah" to
  "aarch64-enable-blah" and update the tests accordingly
* run clang-format on their declarations
* move all these declarations to a common place (the TargetMachine) as opposed
  to having them scattered around (AArch64BranchRelaxation and
  AArch64AddressTypePromotion were the only offenders)

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@277322 91177308-0d34-0410-b5e6-96231b3b80d8
67 files changed:
lib/Target/AArch64/AArch64.h
lib/Target/AArch64/AArch64A53Fix835769.cpp
lib/Target/AArch64/AArch64A57FPLoadBalancing.cpp
lib/Target/AArch64/AArch64AddressTypePromotion.cpp
lib/Target/AArch64/AArch64AdvSIMDScalarPass.cpp
lib/Target/AArch64/AArch64BranchRelaxation.cpp
lib/Target/AArch64/AArch64CleanupLocalDynamicTLSPass.cpp
lib/Target/AArch64/AArch64CollectLOH.cpp
lib/Target/AArch64/AArch64ConditionOptimizer.cpp
lib/Target/AArch64/AArch64ConditionalCompares.cpp
lib/Target/AArch64/AArch64DeadRegisterDefinitionsPass.cpp
lib/Target/AArch64/AArch64PromoteConstant.cpp
lib/Target/AArch64/AArch64RedundantCopyElimination.cpp
lib/Target/AArch64/AArch64StorePairSuppress.cpp
lib/Target/AArch64/AArch64TargetMachine.cpp
test/CodeGen/AArch64/aarch64-gep-opt.ll
test/CodeGen/AArch64/aarch64-loop-gep-opt.ll
test/CodeGen/AArch64/aarch64-stp-cluster.ll
test/CodeGen/AArch64/addsub_ext.ll
test/CodeGen/AArch64/arm64-AdvSIMD-Scalar.ll
test/CodeGen/AArch64/arm64-addr-mode-folding.ll
test/CodeGen/AArch64/arm64-addr-type-promotion.ll
test/CodeGen/AArch64/arm64-ands-bad-peephole.ll
test/CodeGen/AArch64/arm64-arm64-dead-def-elimination-flag.ll
test/CodeGen/AArch64/arm64-big-endian-bitconverts.ll
test/CodeGen/AArch64/arm64-big-endian-vector-callee.ll
test/CodeGen/AArch64/arm64-big-endian-vector-caller.ll
test/CodeGen/AArch64/arm64-ccmp-heuristics.ll
test/CodeGen/AArch64/arm64-ccmp.ll
test/CodeGen/AArch64/arm64-collect-loh-garbage-crash.ll
test/CodeGen/AArch64/arm64-collect-loh-str.ll
test/CodeGen/AArch64/arm64-collect-loh.ll
test/CodeGen/AArch64/arm64-cse.ll
test/CodeGen/AArch64/arm64-early-ifcvt.ll
test/CodeGen/AArch64/arm64-fp128.ll
test/CodeGen/AArch64/arm64-frame-index.ll
test/CodeGen/AArch64/arm64-neon-add-sub.ll
test/CodeGen/AArch64/arm64-promote-const.ll
test/CodeGen/AArch64/arm64-stp-aa.ll
test/CodeGen/AArch64/arm64-stp.ll
test/CodeGen/AArch64/arm64-xaluo.ll
test/CodeGen/AArch64/blockaddress.ll
test/CodeGen/AArch64/breg.ll
test/CodeGen/AArch64/cmp-const-max.ll
test/CodeGen/AArch64/directcond.ll
test/CodeGen/AArch64/fast-isel-branch_weights.ll
test/CodeGen/AArch64/fast-isel-cbz.ll
test/CodeGen/AArch64/fast-isel-cmp-branch.ll
test/CodeGen/AArch64/fast-isel-cmp-vec.ll
test/CodeGen/AArch64/fast-isel-int-ext2.ll
test/CodeGen/AArch64/fast-isel-tbz.ll
test/CodeGen/AArch64/flags-multiuse.ll
test/CodeGen/AArch64/gep-nullptr.ll
test/CodeGen/AArch64/global-merge-1.ll
test/CodeGen/AArch64/global-merge-2.ll
test/CodeGen/AArch64/global-merge-3.ll
test/CodeGen/AArch64/global-merge-4.ll
test/CodeGen/AArch64/global-merge-group-by-use.ll
test/CodeGen/AArch64/global-merge-ignore-single-use-minsize.ll
test/CodeGen/AArch64/global-merge-ignore-single-use.ll
test/CodeGen/AArch64/jump-table.ll
test/CodeGen/AArch64/ldp-stp-scaled-unscaled-pairs.ll
test/CodeGen/AArch64/ldst-opt.ll
test/CodeGen/AArch64/sibling-call.ll
test/CodeGen/AArch64/tailcall-explicit-sret.ll
test/CodeGen/AArch64/tailcall-implicit-sret.ll
test/CodeGen/AArch64/tst-br.ll