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[PowerPC][Future] Add prefixed instruction paddi to future CPU
authorVictor Huang <wei.huang@ibm.com>
Thu, 23 Jan 2020 20:01:02 +0000 (14:01 -0600)
committerVictor Huang <wei.huang@ibm.com>
Fri, 24 Jan 2020 13:27:25 +0000 (07:27 -0600)
commit5cee34013cfd4edea0041bc0b73121cc4ad76ccf
tree6512b657b92f21fbaecbf0c914cd274422343232
parent06ae3748db8a23568f2f238a9534ea9052725ea3
[PowerPC][Future] Add prefixed instruction paddi to future CPU

Future CPU will include support for prefixed instructions.
These prefixed instructions are formed by a 4 byte prefix
immediately followed by a 4 byte instruction effectively
making an 8 byte instruction. The new instruction paddi
is a prefixed form of addi.

This patch adds paddi and all of the support required
for that instruction. The majority of the patch deals with
supporting the new prefixed instructions. The addition of
paddi is mainly to allow for testing.

Differential Revision: https://reviews.llvm.org/D72569
18 files changed:
llvm/lib/Target/PowerPC/AsmParser/PPCAsmParser.cpp
llvm/lib/Target/PowerPC/Disassembler/PPCDisassembler.cpp
llvm/lib/Target/PowerPC/MCTargetDesc/PPCInstPrinter.cpp
llvm/lib/Target/PowerPC/MCTargetDesc/PPCInstPrinter.h
llvm/lib/Target/PowerPC/MCTargetDesc/PPCMCCodeEmitter.cpp
llvm/lib/Target/PowerPC/MCTargetDesc/PPCMCCodeEmitter.h
llvm/lib/Target/PowerPC/PPC.td
llvm/lib/Target/PowerPC/PPCInstrFormats.td
llvm/lib/Target/PowerPC/PPCInstrInfo.h
llvm/lib/Target/PowerPC/PPCInstrInfo.td
llvm/lib/Target/PowerPC/PPCInstrPrefix.td [new file with mode: 0644]
llvm/lib/Target/PowerPC/PPCScheduleP9.td
llvm/lib/Target/PowerPC/PPCSubtarget.cpp
llvm/lib/Target/PowerPC/PPCSubtarget.h
llvm/test/CodeGen/PowerPC/future-check-features.ll [new file with mode: 0644]
llvm/test/MC/Disassembler/PowerPC/future-invalid.txt [new file with mode: 0644]
llvm/test/MC/Disassembler/PowerPC/futureinsts.txt [new file with mode: 0644]
llvm/test/MC/PowerPC/future.s [new file with mode: 0644]