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target/riscv: fix vs() to return proper error code
authorFrank Chang <frank.chang@sifive.com>
Tue, 23 Feb 2021 06:59:32 +0000 (14:59 +0800)
committerAlistair Francis <alistair.francis@wdc.com>
Tue, 23 Mar 2021 01:54:40 +0000 (21:54 -0400)
commit5e437d3ccdccfd85f6e69ca60f921be2dab62c3c
tree443640a16e3517dfffd84c19dd49fff02ee46979
parentc95bd5ff1660883d15ad6e0005e4c8571604f51a
target/riscv: fix vs() to return proper error code

vs() should return -RISCV_EXCP_ILLEGAL_INST instead of -1 if rvv feature
is not enabled.

If -1 is returned, exception will be raised and cs->exception_index will
be set to the negative return value. The exception will then be treated
as an instruction access fault instead of illegal instruction fault.

Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20210223065935.20208-1-frank.chang@sifive.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
target/riscv/csr.c