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[SVE][CodeGen] Legalisation of unpredicated load instructions
authorKerry McLaughlin <kerry.mclaughlin@arm.com>
Tue, 7 Jul 2020 09:35:41 +0000 (10:35 +0100)
committerKerry McLaughlin <kerry.mclaughlin@arm.com>
Tue, 7 Jul 2020 10:05:03 +0000 (11:05 +0100)
commit5e8084beba20f27ce14536168087e5c6971e292d
tree354e2505e2dfc6f81721f034807f182a82fb0d18
parent8c2a613976075368a1f6e3ac3c9c8b1927b465ec
[SVE][CodeGen] Legalisation of unpredicated load instructions

Summary:
When splitting a load of a scalable type, the new address is
calculated in SplitVecRes_LOAD using a vscale and an add instruction.

This patch also adds a DAG combiner fold to visitADD for vscale:
 - Fold (add (vscale(C0)), (vscale(C1))) to (add (vscale(C0 + C1)))

Reviewers: sdesmalen, efriedma, david-arm

Reviewed By: david-arm

Subscribers: tschuett, hiraditya, rkruppe, psnobl, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D82792
llvm/include/llvm/CodeGen/SelectionDAG.h
llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
llvm/test/CodeGen/AArch64/sve-split-load.ll [new file with mode: 0644]