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(parent: 1c7ab5a) | patch
drm/i915/snps: use div32 version of MPLLB word clock for UHBR
authorJani Nikula <jani.nikula@intel.com>
Thu, 2 Dec 2021 14:44:56 +0000 (16:44 +0200)
committerJani Nikula <jani.nikula@intel.com>
Tue, 7 Dec 2021 08:41:07 +0000 (10:41 +0200)
commit61b98486e4314d39d43921680d68b46c3083b22e
tree2b5946145b0f9af8df90a8c999542b2ffca2f8f5tree | snapshot
parent1c7ab5affa5e73ed75732be2f2fabe1ae86c82e1commit | diff
drm/i915/snps: use div32 version of MPLLB word clock for UHBR

The mode set sequence for 128b/132b requires setting the div32 version
of MPLLB clock.

Bspec: 53880, 54128
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20211202144456.2541305-1-jani.nikula@intel.com
drivers/gpu/drm/i915/display/intel_snps_phy.c diff | blob | history
drivers/gpu/drm/i915/i915_reg.h diff | blob | history
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