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[AArch64][TableGen] Skip tied result operands for InstAlias
authorAmara Emerson <amara.emerson@arm.com>
Wed, 8 Feb 2017 11:28:08 +0000 (11:28 +0000)
committerAmara Emerson <amara.emerson@arm.com>
Wed, 8 Feb 2017 11:28:08 +0000 (11:28 +0000)
commit61d1158138aca0fe46a1414184df74ac390af985
tree1bc7d848bb56cd98992bae705172fc3f85ff89ed
parentc049705ee82a1695aa05e61f8bd63d73fd84778c
[AArch64][TableGen] Skip tied result operands for InstAlias

This patch checks the number of operands in the resulting
instruction instead of just the alias, then skips over
tied operands when generating the printing method.

This allows us to generate the preferred assembly syntax
for the AArch64 'ins' instruction, which should always be
displayed as 'mov' according to the ARMARM.

Several unit tests have changed as a result, but only to
reflect the preferred disassembly.

Some other InstAlias patterns (movk/bic/orr) needed a
slight adjustment to stop them becoming the default
and breaking other unit tests.

Patch by Graham Hunter.

Differential Revision: https://reviews.llvm.org/D29219

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@294437 91177308-0d34-0410-b5e6-96231b3b80d8
24 files changed:
lib/Target/AArch64/AArch64InstrInfo.td
test/CodeGen/AArch64/arm64-AdvSIMD-Scalar.ll
test/CodeGen/AArch64/arm64-build-vector.ll
test/CodeGen/AArch64/arm64-dup.ll
test/CodeGen/AArch64/arm64-indexed-vector-ldst.ll
test/CodeGen/AArch64/arm64-neon-copy.ll
test/CodeGen/AArch64/arm64-smaxv.ll
test/CodeGen/AArch64/arm64-sminv.ll
test/CodeGen/AArch64/arm64-stp.ll
test/CodeGen/AArch64/arm64-umaxv.ll
test/CodeGen/AArch64/arm64-uminv.ll
test/CodeGen/AArch64/arm64-vaddv.ll
test/CodeGen/AArch64/arm64-vcombine.ll
test/CodeGen/AArch64/arm64-vector-insertion.ll
test/CodeGen/AArch64/bitreverse.ll
test/CodeGen/AArch64/concat_vector-scalar-combine.ll
test/CodeGen/AArch64/fp16-v16-instructions.ll
test/CodeGen/AArch64/fp16-v4-instructions.ll
test/CodeGen/AArch64/fp16-v8-instructions.ll
test/CodeGen/AArch64/fp16-vector-shuffle.ll
test/CodeGen/AArch64/vector-fcopysign.ll
test/MC/AArch64/arm64-advsimd.s
test/MC/Disassembler/AArch64/arm64-advsimd.txt
utils/TableGen/AsmWriterEmitter.cpp