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(parent: 1aefd61) | patch
nvc0/ir: add support for 64-bit shift lowering on SM20/SM30
authorIlia Mirkin <imirkin@alum.mit.edu>
Sun, 5 Feb 2017 15:03:53 +0000 (10:03 -0500)
committerIlia Mirkin <imirkin@alum.mit.edu>
Thu, 9 Feb 2017 17:57:48 +0000 (12:57 -0500)
commit61d7676df779829e713cdbc2569f7ab50492078d
tree6da0bac9aa7a8ac74c2a9444154a86aac00a5dcetree | snapshot
parent1aefd6159c07cd5b646ce99afd96d4500020418acommit | diff
nvc0/ir: add support for 64-bit shift lowering on SM20/SM30

Unfortunately there is no SHF.L/SHF.R instruction pre-SM35. So we have
to do a bit more work to get the job done.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nvc0.cpp diff | blob | history
external/mesa
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