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RISC-V: Include instruction hex in disassembly
authorMichael Clark <mjc@sifive.com>
Sun, 4 Mar 2018 00:50:12 +0000 (13:50 +1300)
committerMichael Clark <mjc@sifive.com>
Sat, 5 May 2018 22:39:38 +0000 (10:39 +1200)
commit6296a799b14142ccb813b678227ae9e6bf0ffa79
tree54a1f1db84c4c3aef0c18354b9d52b1050add12a
parent42b3a4b7ccbbf419df926939b273fe3b8a6dca1f
RISC-V: Include instruction hex in disassembly

This was added to help debug issues using -d in_asm. It is
useful to see the instruction bytes, as one can detect if
one is trying to execute ASCII or device-tree magic.

Cc: Sagar Karandikar <sagark@eecs.berkeley.edu>
Cc: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Signed-off-by: Michael Clark <mjc@sifive.com>
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
disas/riscv.c