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(parent: 069d418) | patch
drm/amd/display: cache pwl params and scl_data to avoid extra programming
authorDmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Fri, 27 Oct 2017 21:55:03 +0000 (17:55 -0400)
committerAlex Deucher <alexander.deucher@amd.com>
Wed, 6 Dec 2017 17:47:28 +0000 (12:47 -0500)
commit6334ac93a1e1ff8b99dac98bb7ef790b5786ea3c
tree364fed24cbacf1ba11c87387c1d39168e4a5685btree | snapshot
parent069d418f412ec4b33056dc7d84b63c80c2e50abfcommit | diff
drm/amd/display: cache pwl params and scl_data to avoid extra programming

This saves us about 5000 reg writes per full update. This translates to about
40000 writes over the course of single eDP bootup.

Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.c diff | blob | history
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp.h diff | blob | history
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dpp_dscl.c diff | blob | history
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c diff | blob | history
drivers/gpu/drm/amd/display/dc/inc/hw/dpp.h diff | blob | history
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