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AMDGPU/GlobalISel: Select G_SHL
authorMatt Arsenault <Matthew.Arsenault@amd.com>
Tue, 16 Jul 2019 20:15:30 +0000 (20:15 +0000)
committerMatt Arsenault <Matthew.Arsenault@amd.com>
Tue, 16 Jul 2019 20:15:30 +0000 (20:15 +0000)
commit65c12193d047638b182e7e954f56304a6b2b3b3d
treeebb71b7e865ef1a9bb51918dd80f8fcda395bdfatree | snapshot
parent10f786ca0ffdabfacd9ea60168488ee16d95c7e4commit | diff
AMDGPU/GlobalISel: Select G_SHL

I think this manages to not break the DAG handling with the divergent
predicates because the stadalone divergent patterns end up with a
higher priority than the pattern on the instruction definition.

The 16-bit versions don't work yet.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@366254 91177308-0d34-0410-b5e6-96231b3b80d8
lib/Target/AMDGPU/SOPInstructions.td diff | blob | history
lib/Target/AMDGPU/VOP2Instructions.td diff | blob | history
lib/Target/AMDGPU/VOP3Instructions.td diff | blob | history
test/CodeGen/AMDGPU/GlobalISel/inst-select-shl.mir [new file with mode: 0644] blob
test/CodeGen/AMDGPU/GlobalISel/inst-select-shl.s16.mir [new file with mode: 0644] blob
test/CodeGen/AMDGPU/GlobalISel/inst-select-shl.v2s16.mir [new file with mode: 0644] blob
external/llvm
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