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AMDGPU/SI: Fix visit order assumption in SIFixSGPRCopies
authorTom Stellard <thomas.stellard@amd.com>
Fri, 11 Nov 2016 23:35:42 +0000 (23:35 +0000)
committerTom Stellard <thomas.stellard@amd.com>
Fri, 11 Nov 2016 23:35:42 +0000 (23:35 +0000)
commit6687aabcf555bf38c9029fdf03c217fe17c70a3c
treedd37b094ef4b482d957f5cae6a5b981c48a44218
parentd085da51ef09a195fe3e9f6a112be52bc0904090
AMDGPU/SI: Fix visit order assumption in SIFixSGPRCopies

Summary:
This pass was assuming that when a PHI instruction defined a register
used by another PHI instruction that the defining insstruction would
be legalized before the using instruction.

This assumption was causing the pass to not legalize some PHI nodes
within divergent flow-control.

This fixes a bug that was uncovered by r285762.

Reviewers: nhaehnle, arsenm

Subscribers: kzhuravl, wdng, nhaehnle, yaxunl, tony-tye, llvm-commits

Differential Revision: https://reviews.llvm.org/D26303

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@286676 91177308-0d34-0410-b5e6-96231b3b80d8
lib/Target/AMDGPU/SIFixSGPRCopies.cpp
test/CodeGen/AMDGPU/salu-to-valu.ll
test/CodeGen/MIR/AMDGPU/si-fix-sgpr-copies.mir [new file with mode: 0644]