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(parent: 6f6178f) | patch
clk: renesas: r9a07g044: Add DSI clock and reset entries
authorBiju Das <biju.das.jz@bp.renesas.com>
Sat, 30 Apr 2022 11:41:56 +0000 (12:41 +0100)
committerGeert Uytterhoeven <geert+renesas@glider.be>
Thu, 5 May 2022 10:10:21 +0000 (12:10 +0200)
commit67f80edf8390fd8201bb285fe2b55df9e2e5edbe
treea8a0881f7c42f85bb082e0439ae1e39edecaa687tree | snapshot
parent6f6178f1e1250d959ef19f408f0e392ea29de665commit | diff
clk: renesas: r9a07g044: Add DSI clock and reset entries

Add DSI clock and reset entries to CPG driver.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Link: https://lore.kernel.org/r/20220430114156.6260-10-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
drivers/clk/renesas/r9a07g044-cpg.c diff | blob | history
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