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MachineFunctionProperties/MIRParser: Rename AllVRegsAllocated->NoVRegs, compute it
authorMatthias Braun <matze@braunis.de>
Thu, 25 Aug 2016 01:27:13 +0000 (01:27 +0000)
committerMatthias Braun <matze@braunis.de>
Thu, 25 Aug 2016 01:27:13 +0000 (01:27 +0000)
commit690a3cbc95109c1125ca61e8001d738e6e50ab74
tree7b9f4d20f90e6afaa9e59486795a4e6e66f04a30
parentcf1269a0b2657ed42f3d1632fcf1790fcfb0741b
MachineFunctionProperties/MIRParser: Rename AllVRegsAllocated->NoVRegs, compute it

Rename AllVRegsAllocated to NoVRegs. This avoids the connotation of
running after register and simply describes that no vregs are used in
a machine function. With that we can simply compute the property and do
not need to dump/parse it in .mir files.

Differential Revision: http://reviews.llvm.org/D23850

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@279698 91177308-0d34-0410-b5e6-96231b3b80d8
79 files changed:
include/llvm/CodeGen/MIRYamlMapping.h
include/llvm/CodeGen/MachineFunction.h
lib/CodeGen/ExecutionDepsFix.cpp
lib/CodeGen/FuncletLayout.cpp
lib/CodeGen/IfConversion.cpp
lib/CodeGen/ImplicitNullChecks.cpp
lib/CodeGen/LiveDebugValues.cpp
lib/CodeGen/MIRParser/MIRParser.cpp
lib/CodeGen/MIRPrinter.cpp
lib/CodeGen/MachineCopyPropagation.cpp
lib/CodeGen/MachineFunction.cpp
lib/CodeGen/MachineVerifier.cpp
lib/CodeGen/PatchableFunction.cpp
lib/CodeGen/PostRASchedulerList.cpp
lib/CodeGen/PrologEpilogInserter.cpp
lib/CodeGen/RegAllocFast.cpp
lib/CodeGen/StackMapLivenessAnalysis.cpp
lib/CodeGen/VirtRegMap.cpp
lib/Target/AArch64/AArch64A53Fix835769.cpp
lib/Target/AArch64/AArch64A57FPLoadBalancing.cpp
lib/Target/AArch64/AArch64CollectLOH.cpp
lib/Target/AArch64/AArch64DeadRegisterDefinitionsPass.cpp
lib/Target/AArch64/AArch64LoadStoreOptimizer.cpp
lib/Target/AArch64/AArch64RedundantCopyElimination.cpp
lib/Target/ARM/ARMConstantIslandPass.cpp
lib/Target/ARM/ARMExpandPseudoInsts.cpp
lib/Target/ARM/ARMLoadStoreOptimizer.cpp
lib/Target/ARM/ARMOptimizeBarriersPass.cpp
lib/Target/ARM/Thumb2ITBlockPass.cpp
lib/Target/ARM/Thumb2SizeReduction.cpp
lib/Target/Hexagon/HexagonCFGOptimizer.cpp
lib/Target/Hexagon/HexagonCopyToCombine.cpp
lib/Target/Hexagon/HexagonFixupHwLoops.cpp
lib/Target/Hexagon/HexagonFrameLowering.cpp
lib/Target/Hexagon/HexagonGenMux.cpp
lib/Target/Hexagon/HexagonNewValueJump.cpp
lib/Target/Hexagon/HexagonRDFOpt.cpp
lib/Target/Hexagon/HexagonSplitConst32AndConst64.cpp
lib/Target/Hexagon/HexagonVLIWPacketizer.cpp
lib/Target/Lanai/LanaiDelaySlotFiller.cpp
lib/Target/Lanai/LanaiMemAluCombiner.cpp
lib/Target/MSP430/MSP430BranchSelector.cpp
lib/Target/Mips/MipsConstantIslandPass.cpp
lib/Target/Mips/MipsDelaySlotFiller.cpp
lib/Target/Mips/MipsHazardSchedule.cpp
lib/Target/Mips/MipsLongBranch.cpp
lib/Target/PowerPC/PPCBranchSelector.cpp
lib/Target/PowerPC/PPCEarlyReturn.cpp
lib/Target/Sparc/DelaySlotFiller.cpp
lib/Target/SystemZ/SystemZElimCompare.cpp
lib/Target/SystemZ/SystemZLongBranch.cpp
lib/Target/SystemZ/SystemZShortenInst.cpp
lib/Target/WebAssembly/WebAssemblyTargetMachine.cpp
lib/Target/X86/X86ExpandPseudo.cpp
lib/Target/X86/X86FixupBWInsts.cpp
lib/Target/X86/X86FixupLEAs.cpp
lib/Target/X86/X86FloatingPoint.cpp
lib/Target/X86/X86PadShortFunction.cpp
lib/Target/X86/X86VZeroUpper.cpp
lib/Target/XCore/XCoreFrameToArgsOffsetElim.cpp
test/CodeGen/AArch64/ldst-opt-dbg-limit.mir
test/CodeGen/AArch64/movimm-wzr.mir
test/CodeGen/ARM/ARMLoadStoreDBG.mir
test/CodeGen/Hexagon/ifcvt-impuse-livein.mir
test/CodeGen/MIR/AArch64/inst-size-tlsdesc-callseq.mir
test/CodeGen/MIR/AArch64/machine-dead-copy.mir
test/CodeGen/MIR/ARM/sched-it-debug-nodes.mir
test/CodeGen/MIR/Hexagon/anti-dep-partial.mir
test/CodeGen/MIR/Lanai/peephole-compare.mir
test/CodeGen/PowerPC/aantidep-def-ec.mir
test/CodeGen/PowerPC/addisdtprelha-nonr3.mir
test/CodeGen/PowerPC/opt-sub-inst-cr0-live.mir
test/CodeGen/X86/eflags-copy-expansion.mir
test/CodeGen/X86/fixup-bw-copy.mir
test/CodeGen/X86/implicit-null-checks.mir
test/CodeGen/X86/machine-copy-prop.mir
test/CodeGen/X86/pr27681.mir
test/DebugInfo/MIR/X86/live-debug-values-3preds.mir
test/DebugInfo/MIR/X86/live-debug-values.mir