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author	Craig Topper <craig.topper@intel.com>
	Fri, 17 Jul 2020 05:04:24 +0000 (22:04 -0700)
committer	Craig Topper <craig.topper@intel.com>
	Fri, 17 Jul 2020 05:04:29 +0000 (22:04 -0700)
commit	6bba95831e480656124a5fbcd84f4f2a31e6c0b6
tree	aaa57d531c5135c971b06394a2633db14d888d51	tree \| snapshot
parent	addbf732c83b54259d6aa2c6ed982099be0aeeaf	commit \| diff

[X86] Change the scheduler model for 'pentium4' to SandyBridgeModel.

I meant to do this in D83913, but missed it while updating the
feature list.

Interestingly I think this is disabling the postRA scheduler. But
it does match our default 64-bit behavior.

Reviewed By: echristo

Differential Revision: https://reviews.llvm.org/D83996

external/llvm-project

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llvm/lib/Target/X86/X86.td		diff \| blob \| history
llvm/test/CodeGen/X86/cfguard-x86-vectorcall.ll		diff \| blob \| history
llvm/test/CodeGen/X86/cmov-fp.ll		diff \| blob \| history
llvm/test/CodeGen/X86/post-ra-sched.ll		diff \| blob \| history
llvm/test/CodeGen/X86/pr34088.ll		diff \| blob \| history
llvm/test/CodeGen/X86/pr40539.ll		diff \| blob \| history
llvm/test/DebugInfo/COFF/fpo-stack-protect.ll		diff \| blob \| history