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target-arm: A64: add support for 2-src shift reg insns
authorAlexander Graf <agraf@suse.de>
Tue, 17 Dec 2013 19:42:34 +0000 (19:42 +0000)
committerPeter Maydell <peter.maydell@linaro.org>
Tue, 17 Dec 2013 20:12:51 +0000 (20:12 +0000)
commit6c1adc919b6a81e008b919c53902b4877ef4d737
treeedb74edb6dc56584905e243cd18dd773eadf23a8tree | snapshot
parent8220e911c240df5b4b2a1473f0ba9feddc154c45commit | diff
target-arm: A64: add support for 2-src shift reg insns

This adds 2-src variable shift register instructions:
C5.6.115 LSLV, C5.6.118 LSRV, C5.6.17 ASRV, C5.6.154 RORV

Signed-off-by: Alexander Graf <agraf@suse.de>
[claudio: adapted to new decoder, use enums for shift types]
Signed-off-by: Claudio Fontana <claudio.fontana@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <rth@twiddle.net>
target-arm/translate-a64.c diff | blob | history
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