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target/riscv: correct "code should not be reached" for x-rv128
authorFrédéric Pétrot <frederic.petrot@univ-grenoble-alpes.fr>
Mon, 24 Jan 2022 20:24:56 +0000 (21:24 +0100)
committerAlistair Francis <alistair.francis@wdc.com>
Wed, 16 Feb 2022 02:24:18 +0000 (12:24 +1000)
commit6c3a9247259940069402ee169e63aac0ac5f8f6b
treed3f20540d92cfa7f85cae3fc0c8a820dcd11fcae
parentf42483d776bce29a9925ed61cc10eb27a5b2446c
target/riscv: correct "code should not be reached" for x-rv128

The addition of uxl support in gdbstub adds a few checks on the maximum
register length, but omitted MXL_RV128, an experimental feature.
This patch makes rv128 react as rv64, as previously.

Signed-off-by: Frédéric Pétrot <frederic.petrot@univ-grenoble-alpes.fr>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20220124202456.420258-1-frederic.petrot@univ-grenoble-alpes.fr
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
target/riscv/cpu.c
target/riscv/gdbstub.c