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clk: sunxi: Add apb0 gates for H3
authorKrzysztof Adamski <k@japko.eu>
Mon, 22 Feb 2016 13:03:25 +0000 (14:03 +0100)
committerMaxime Ripard <maxime.ripard@free-electrons.com>
Thu, 25 Feb 2016 19:30:32 +0000 (11:30 -0800)
commit6e17b4181603d183d20c73f4535529ddf2a2a020
treea955d26015816ed7e2d23937fe1e4bb731fd4908
parentd331328da6b719e4ffb3b43125bbe540755239ad
clk: sunxi: Add apb0 gates for H3

This patch adds support for APB0 in H3. It seems to be compatible with
earlier SOCs. apb0 gates controls R_ block peripherals (R_PIO, R_IR,
etc).

Since this gates behave just like any Allwinner clock gate, add a generic
compatible that can be reused if we don't have any clock to protect.

Signed-off-by: Krzysztof Adamski <k@japko.eu>
[Maxime: Removed the H3 compatible from the simple-gates driver, reworked
         the commit log a bit]
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Documentation/devicetree/bindings/clock/sunxi.txt
drivers/clk/sunxi/clk-simple-gates.c