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arm64: dts: renesas: r8a77990: Add secondary CA53 CPU core
authorGeert Uytterhoeven <geert+renesas@glider.be>
Tue, 5 Jun 2018 17:17:13 +0000 (19:17 +0200)
committerSimon Horman <horms+renesas@verge.net.au>
Mon, 25 Jun 2018 13:30:27 +0000 (15:30 +0200)
commit7085f5d9e803688045e92ccb69e1f7fe0eee9621
tree3107fc4f263613165590c9ab912ff328c50493bdtree | snapshot
parenteb614d94395293da7beecaa29555acb8966a2796commit | diff
arm64: dts: renesas: r8a77990: Add secondary CA53 CPU core

Add a device node for the second Cortex-A53 CPU core on the Renesas
R-Car E3 (r8a77990) SoC, and adjust the interrupt delivery masks for ARM
Generic Interrupt Controller and Architectured Timer.

Based on a patch in the BSP by Takeshi Kihara.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
arch/arm64/boot/dts/renesas/r8a77990.dtsi diff | blob | history
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