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drm/amd/display: Fix register definitions for DCN32/321
authorAurabindo Pillai <aurabindo.pillai@amd.com>
Thu, 1 Sep 2022 19:27:36 +0000 (15:27 -0400)
committerAlex Deucher <alexander.deucher@amd.com>
Tue, 13 Sep 2022 18:33:00 +0000 (14:33 -0400)
commit70c04ad8441a60ee65ca2e1c40fac04882ba09f8
treed712214acfb9a24527f77e6fbdd9242ed23995c0
parent410e747401a3121cffba6ecb932f5df596799550
drm/amd/display: Fix register definitions for DCN32/321

[Why & How]
Fix the instatiation sequence for MPC registers and add a few other
missing register definitions that were ommited erroneously when copying
them over to enable runtime initialization of reigster offsets for
DCN32/321

Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Reviewed-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Signed-off-by: Aurabindo Pillai <aurabindo.pillai@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.c
drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.h
drivers/gpu/drm/amd/display/dc/dcn321/dcn321_resource.c