[AArch64] Extend single-operand FP insns to match Arm ARM (NFCI)

[AArch64] Extend single-operand FP insns to match Arm ARM (NFCI)

The Armv8.3-A reference manual defines floating-point data-processing
instructions with one source operand to have an opcode of 6 bits
[20:15]. The current class in tablegen, BaseSingleOperandFPData, only
allows [18:15]. This was ok because [20:19] could only be '00', with
other encodings unallocated. Armv8.5-A brings in the FRINT group of
instructions which use other values for these bits.

This patch refactors the existing class a bit to allow using the full 6
bits of the opcode, as defined in the Arm ARM.

Patch by Pablo Barrio!

Differential revision: https://reviews.llvm.org/D52474

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@343120 91177308-0d34-0410-b5e6-96231b3b80d8