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drm/i915/tgl: Use refclk/2 as bypass frequency
authorMatt Roper <matthew.d.roper@intel.com>
Thu, 5 Sep 2019 18:13:37 +0000 (11:13 -0700)
committerMatt Roper <matthew.d.roper@intel.com>
Fri, 6 Sep 2019 15:42:13 +0000 (08:42 -0700)
commit71cd86cfaa12645ca39e5bbeceb2039af74fba2e
tree2ab0eb651f8fca118e2b1016c42e4f114456a4c3
parentca9cab183449787058f700fd0a74a8c91b277268
drm/i915/tgl: Use refclk/2 as bypass frequency

Unlike gen11, which always ran at 50MHz when the cdclk PLL was disabled,
TGL runs at refclk/2.  The 50MHz croclk/2 is only used by hardware
during some power state transitions.

Bspec: 49201
Cc: José Roberto de Souza <jose.souza@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20190905181337.23727-1-matthew.d.roper@intel.com
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
drivers/gpu/drm/i915/display/intel_cdclk.c