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clk: ingenic/jz4725b: Fix incorrect dividers for main clocks
authorPaul Cercueil <paul@crapouillou.net>
Thu, 2 May 2019 21:25:01 +0000 (23:25 +0200)
committerStephen Boyd <sboyd@kernel.org>
Fri, 7 Jun 2019 18:49:01 +0000 (11:49 -0700)
commit74054c413ae8c36a5529e7891c2450a747667753
tree0c52bedcaa173d80e608b33bc069eb46a545614d
parent44b06a76ad330f327fe2366472a83d7d1d06d86e
clk: ingenic/jz4725b: Fix incorrect dividers for main clocks

The main clocks (cclk, hclk, pclk, mclk, ipu) were using
incorrect dividers, and thus reported an incorrect rate.

Signed-off-by: Paul Cercueil <paul@crapouillou.net>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
drivers/clk/ingenic/jz4725b-cgu.c