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[X86][SSE] Add MINSD/MAXSD/MINSS/MAXSS intrinsic scalar load folding support
authorSimon Pilgrim <llvm-dev@redking.me.uk>
Wed, 24 Aug 2016 18:40:53 +0000 (18:40 +0000)
committerSimon Pilgrim <llvm-dev@redking.me.uk>
Wed, 24 Aug 2016 18:40:53 +0000 (18:40 +0000)
commit7432a84aecd2dc5a0e45e06209b1b3097ddbd1c7
treebb9bf30ea229c5f1cbb59859eccb1476f88db6eatree | snapshot
parentbf471b7adc6ab5b69b2515f09ed73fad955954cbcommit | diff
[X86][SSE] Add MINSD/MAXSD/MINSS/MAXSS intrinsic scalar load folding support

These are no different in load behaviour to the existing ADD/SUB/MUL/DIV scalar ops but were missing from isNonFoldablePartialRegisterLoad

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@279652 91177308-0d34-0410-b5e6-96231b3b80d8
lib/Target/X86/X86InstrInfo.cpp diff | blob | history
test/CodeGen/X86/vec_ss_load_fold.ll diff | blob | history
external/llvm
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