OSDN Git Service

[X86] Change register&memory TEST instructions from MRMSrcMem to MRMDstMem
authorCraig Topper <craig.topper@intel.com>
Sun, 1 Oct 2017 23:53:53 +0000 (23:53 +0000)
committerCraig Topper <craig.topper@intel.com>
Sun, 1 Oct 2017 23:53:53 +0000 (23:53 +0000)
commit7525c7b0755ec5c4e81392772dac094855381594
treeada4fdb8ee37f3b95fa6e8f3f22849ddd8d258f7
parent5875fb148311e0747b91e00b5f64ded1d3971be0
[X86] Change register&memory TEST instructions from MRMSrcMem to MRMDstMem

Summary:
Intel documentation shows the memory operand as the first operand. But we currently treat it as the second operand. Conceptually the order doesn't matter since it doesn't write memory. We have aliases to parse with the operands in either order and the isel matching is commutable.

For the register&register form order does matter for the assembly parser. PR22995 was previously filed and fixed by changing the register&register form from MRMSrcReg to MRMDestReg to match gas. Ideally the memory form should match by using MRMDestMem.

I believe this supercedes D38025 which was trying to switch the register&register form back to pre-PR22995.

Reviewers: aymanmus, RKSimon, zvi

Reviewed By: aymanmus

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D38120

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@314639 91177308-0d34-0410-b5e6-96231b3b80d8
15 files changed:
lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp
lib/Target/X86/X86InstrArithmetic.td
lib/Target/X86/X86InstrInfo.cpp
lib/Target/X86/X86InstrInfo.td
lib/Target/X86/X86MacroFusion.cpp
lib/Target/X86/X86SchedHaswell.td
lib/Target/X86/X86SchedSandyBridge.td
lib/Target/X86/X86SchedSkylakeClient.td
test/CodeGen/X86/absolute-bit-mask.ll
test/CodeGen/X86/post-ra-sched-with-debug.mir
test/CodeGen/X86/testl-commute.ll
test/MC/Disassembler/X86/x86-16.txt
test/MC/X86/intel-syntax.s
test/MC/X86/x86-16.s
test/MC/X86/x86-32.s