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[X86][SandyBridge] SBWriteResPair +5cy Memory Folds
authorSimon Pilgrim <llvm-dev@redking.me.uk>
Fri, 6 Apr 2018 11:00:51 +0000 (11:00 +0000)
committerSimon Pilgrim <llvm-dev@redking.me.uk>
Fri, 6 Apr 2018 11:00:51 +0000 (11:00 +0000)
commit770176590e3a3216c39de2afd43912a66a275385
treeffa8d006bcf4dece000217b409cc9579b5d9a5fc
parent2d9c75def2d1a4e650d14358715ea7e1584c42a9
[X86][SandyBridge] SBWriteResPair +5cy Memory Folds

As mentioned on D44647, this patch increases the default memory latency to +5cy , which more closely matches what most custom cases are doing for reg-mem instructions.

I've bumped LoadLatency, ReadAfterLd and WriteLoad values to 5cy to be consistent.

As Sandy Bridge is currently our default generic model, this affects a lot of scheduling tests...

Differential Revision: https://reviews.llvm.org/D44654

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@329388 91177308-0d34-0410-b5e6-96231b3b80d8
23 files changed:
lib/Target/X86/X86SchedSandyBridge.td
test/CodeGen/X86/3dnow-schedule.ll
test/CodeGen/X86/adx-schedule.ll
test/CodeGen/X86/avx-schedule.ll
test/CodeGen/X86/avx2-schedule.ll
test/CodeGen/X86/avx512-schedule.ll
test/CodeGen/X86/avx512-shuffle-schedule.ll
test/CodeGen/X86/avx512vpopcntdq-schedule.ll
test/CodeGen/X86/bmi-schedule.ll
test/CodeGen/X86/bmi2-schedule.ll
test/CodeGen/X86/clwb-schedule.ll
test/CodeGen/X86/f16c-schedule.ll
test/CodeGen/X86/fma-schedule.ll
test/CodeGen/X86/fma4-schedule.ll
test/CodeGen/X86/mmx-schedule.ll
test/CodeGen/X86/movbe-schedule.ll
test/CodeGen/X86/schedule-x86_32.ll
test/CodeGen/X86/schedule-x86_64.ll
test/CodeGen/X86/sha-schedule.ll
test/CodeGen/X86/sse41-schedule.ll
test/CodeGen/X86/tbm-schedule.ll
test/CodeGen/X86/x87-schedule.ll
test/CodeGen/X86/xop-schedule.ll