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arm64: dts: qcom: sm8350: Fix level triggered PMU interrupt polarity
authorSai Prakash Ranjan <saiprakash.ranjan@codeaurora.org>
Tue, 16 Feb 2021 09:47:48 +0000 (15:17 +0530)
committerBjorn Andersson <bjorn.andersson@linaro.org>
Fri, 12 Mar 2021 02:22:39 +0000 (20:22 -0600)
commit794d3e309e44c99158d0166b1717f297341cf3ab
tree9b8defe129d5e77e68527d79db4e36ac8dc2a796tree | snapshot
parent93138ef5ac923b10f81575d35dbcb83136cbfc40commit | diff
arm64: dts: qcom: sm8350: Fix level triggered PMU interrupt polarity

As per interrupt documentation for SM8350 SoC, the polarity
for level triggered PMU interrupt is low, fix this.

Fixes: b7e8f433a673 ("arm64: dts: qcom: Add basic devicetree support for SM8350 SoC")
Signed-off-by: Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org>
Link: https://lore.kernel.org/r/ca57409198477f7815e32a6a7467dcdc9b93dc4f.1613468366.git.saiprakash.ranjan@codeaurora.org
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
arch/arm64/boot/dts/qcom/sm8350.dtsi diff | blob | history
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