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[Power9] Builtins for ELF v.2 API conformance - back end portion
authorNemanja Ivanovic <nemanja.i.ibm@gmail.com>
Tue, 27 Sep 2016 08:42:12 +0000 (08:42 +0000)
committerNemanja Ivanovic <nemanja.i.ibm@gmail.com>
Tue, 27 Sep 2016 08:42:12 +0000 (08:42 +0000)
commit7a5ffa38827203b8f815b9f48d33fd3088d6b4c2
tree4a59dd7bd1a948ced5b7226752116d923040c517
parent941593b0ca91a3e4d85b3134ae7228c6cb45e25b
[Power9] Builtins for ELF v.2 API conformance - back end portion

This patch corresponds to review:
https://reviews.llvm.org/D24396

This patch adds support for the "vector count trailing zeroes",
"vector compare not equal" and "vector compare not equal or zero instructions"
as well as "scalar count trailing zeroes" instructions. It also changes the
vector negation to use XXLNOR (when VSX is enabled) so as not to increase
register pressure (previously this was done with a splat immediate of all
ones followed by an XXLXOR). This was done because the altivec.h
builtins (patch to follow) use vector negation and the use of an additional
register for the splat immediate is not optimal.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@282478 91177308-0d34-0410-b5e6-96231b3b80d8
include/llvm/IR/IntrinsicsPowerPC.td
lib/Target/PowerPC/PPCISelLowering.cpp
lib/Target/PowerPC/PPCInstrAltivec.td
lib/Target/PowerPC/PPCInstrVSX.td
test/CodeGen/PowerPC/p9-vector-compares-and-counts.ll [new file with mode: 0644]
test/CodeGen/PowerPC/vsx.ll