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GlobalISel: disambiguate types when printing MIR
authorTim Northover <tnorthover@apple.com>
Mon, 12 Sep 2016 11:20:10 +0000 (11:20 +0000)
committerTim Northover <tnorthover@apple.com>
Mon, 12 Sep 2016 11:20:10 +0000 (11:20 +0000)
commit7a92e735b62219292645662d2d1bee77e62423ab
treef507bcb1266c545c6f51b0f01b562daf68d03ad5
parent217343a63acbc767eb5c264a16134cc8c149631c
GlobalISel: disambiguate types when printing MIR

Some generic instructions have multiple types. While in theory these always be
discovered by inspecting the single definition of each generic vreg, in
practice those definitions won't always be local and traipsing through a big
function to find them will not be fun.

So this changes MIRPrinter to print out the type of uses as well as defs, if
they're known to be different or not known to be the same.

On the parsing side, we're a little more flexible: provided each register is
given a type in at least one place it's mentioned (and all types are
consistent) we accept the MIR. This doesn't introduce ambiguity but makes
writing tests manually a bit less painful.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@281204 91177308-0d34-0410-b5e6-96231b3b80d8
13 files changed:
lib/CodeGen/MIRParser/MIParser.cpp
lib/CodeGen/MIRParser/MIRParser.cpp
lib/CodeGen/MIRPrinter.cpp
lib/CodeGen/MachineRegisterInfo.cpp
test/CodeGen/AArch64/GlobalISel/arm64-irtranslator.ll
test/CodeGen/AArch64/GlobalISel/call-translator.ll
test/CodeGen/AArch64/GlobalISel/legalize-cmp.mir
test/CodeGen/AArch64/GlobalISel/legalize-combines.mir
test/CodeGen/AArch64/GlobalISel/legalize-fcmp.mir
test/CodeGen/AArch64/GlobalISel/legalize-load-store.mir
test/CodeGen/AArch64/GlobalISel/legalize-simple.mir
test/CodeGen/MIR/X86/expected-integer-after-tied-def.mir
test/CodeGen/MIR/X86/expected-tied-def-after-lparen.mir