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(parent: cea5fb9) | patch
arm64: Potential rollover condition for timer counter
authorPrasad Sodagudi <psodagud@codeaurora.org>
Thu, 12 Jan 2017 18:11:39 +0000 (10:11 -0800)
committerPrasad Sodagudi <psodagud@codeaurora.org>
Sat, 14 Jan 2017 02:02:42 +0000 (18:02 -0800)
commit7b2f8ee7696e33566aa8e3ed523d70994184c7bc
tree00524a1a9dc343fdff6ac2c532648d1feb0970b2tree | snapshot
parentcea5fb94484444f7acd47c41d165d648a4df29f9commit | diff
arm64: Potential rollover condition for timer counter

There is potential rollover condition for CNTVCT and
CNTPCT counters. So on any architecture timer counter
read, if the least significant 32 bits are set,
reread counter.

CRs-Fixed: 1074621
Change-Id: I136a5f0ee04deeb74c03800d591e44fbd9b4dd39
Signed-off-by: Prasad Sodagudi <psodagud@codeaurora.org>
arch/arm64/include/asm/arch_timer.h diff | blob | history
drivers/clocksource/Kconfig diff | blob | history
Mirror: https://github.com/0ranko0P/kernel_xiaomi_msm8998/
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