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riscv: sifive_u: Fix broken GEM support
authorBin Meng <bmeng.cn@gmail.com>
Fri, 6 Sep 2019 16:20:17 +0000 (09:20 -0700)
committerPalmer Dabbelt <palmer@sifive.com>
Tue, 17 Sep 2019 15:42:49 +0000 (08:42 -0700)
commit7b6bb66f02bc81a6bb5d90a4fe08ab9c6841a936
tree77a74285ccaefa11f79051587f43b8d3e15dfd90
parent5461c4fefed627eac9e1cadfb5754fc985d6df89
riscv: sifive_u: Fix broken GEM support

At present the GEM support in sifive_u machine is seriously broken.
The GEM block register base was set to a weird number (0x100900FC),
which for no way could work with the cadence_gem model in QEMU.

Not like other GEM variants, the FU540-specific GEM has a management
block to control 10/100/1000Mbps link speed changes, that is mapped
to 0x100a0000. We can simply map it into MMIO space without special
handling using create_unimplemented_device().

Update the GEM node compatible string to use the official name used
by the upstream Linux kernel, and add the management block reg base
& size to the <reg> property encoding.

Tested with upstream U-Boot and Linux kernel MACB drivers.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
hw/riscv/Kconfig
hw/riscv/sifive_u.c
include/hw/riscv/sifive_u.h