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drm/i915: Apply batch location restrictions before pinning
authorChris Wilson <chris@chris-wilson.co.uk>
Sun, 10 Jun 2018 19:43:09 +0000 (20:43 +0100)
committerJani Nikula <jani.nikula@intel.com>
Tue, 19 Jun 2018 12:47:37 +0000 (15:47 +0300)
commit7ba33e1c9d1e03f442b161c701d1f811ea13c75e
tree3ae98b64efd0dbf9fc7a3c2ec2243ffda897bbf2
parentce397d215ccd07b8ae3f71db689aedb85d56ab40
drm/i915: Apply batch location restrictions before pinning

We special case the position of the batch within the GTT to prevent
negative self-relocation deltas from underflowing. However, that
restriction is being applied after a trial pin of the batch in its
current position. Thus we are not rejecting an invalid location if the
batch has been used before, leading to an assertion if we happen to need
to rearrange the entire payload. In the worst case, this may cause a GPU
hang on gen7 or perhaps missing state.

References: https://bugs.freedesktop.org/show_bug.cgi?id=105720
Fixes: 2889caa92321 ("drm/i915: Eliminate lots of iterations over the execobjects array")
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Cc: Martin Peres <martin.peres@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20180610194325.13467-2-chris@chris-wilson.co.uk
Reviewed-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
(cherry picked from commit 746c8f143afad7aaa66c484485fc39888d437a3f)
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
drivers/gpu/drm/i915/i915_gem_execbuffer.c